IP Soc Conference in Grenoble

And so I went for my first conference as a VC in making. The conference was aimed at IP integration in System on Chip environments. The world is moving more and more towards multiple processors on chips and integration of IP from different sources, different maturities and at different locations is a challenge. Reminded me of the old days at Philips Semiconductors when I would have to stay up late nights waiting for conference calls with Sunnyvale while I soldered at home.

The talks on the first day were interesting especially that of Jacques Benkoski a Venture Capitalist with US Venture Partners. He mentioned what I've been seeing from Gartner reports i.e. Number of design starts (ASIC and ASSP) are steadily declining but the number of algorithmic engines that will be designed on these chips will grow exponentially. That just means that companies will create more and more derivatives based on a combination of reusable IP. Benkoski broke down IP in three distinct models:

1. Horizontal IP
2. Vertical IP
3. System IP

Horizontal IPs are basic fabrics applicable to a wide range of SoCs providing system level advantages. Take a look at this smart idea.
Vertical IP are application specific IPs, dedicated to enabling the SoC into specific markets segments and are highly differentiated
System level IP leverages itself for designers in all design phases.

I thought that it was a pretty smart classification but what really caught my attention were the following two statements:

1. Semiconductor industry as a whole is growing much slower than before and when looking at IPs one needs to differentiate Unique IPs from Productivity IPs. The unique IPs which have a chance of making it big are those which will not eat into the gross profits of the TI, ST and NXPs of the world. I'm going to do that mental exercise next time I get a Semiconductor Business Plan.
2. The ones who actually make it to first customer reference sales will go through the Lemming effect. After the first high the company will hit a low and only a few wil be able to ride the second crest. It's abit like crossing the chasm an excellent book I read while at Insead. New technology is at first taken aboard by early adopters, in Semiconductors terms by typically small design firms like Pixelworks and only when the early adopters start taping out highly differentiated IPs which earns them really good margins do the big boys buy in.

So what else came out of this conference?

• In Horizontal IPs the start up which enables to reduce leakage current is going to make it really big. Till now design tools and the engineering community has been working on dynamic power reduction. This power depends on frequency with which you move around data and instructions, the capacitive load of drivers on the IC and the square of the Voltage at which blocks run. As long as manufacturing technology was above the 90 nanometres, lazy designers didn't really care about power. Each reduction in technology ( i.e. 200 nm to 130 nm) would have a big impact on the voltage and you'd not really have to worry about power management. But I remember my first real chip design the PNX101 was in 90 nanometres and hey the power benefits from 130 to 90 in terms of voltages was just not enough to meet customer requirements. That's when we started thinking of having different blocks running at different frequencies, clock gating, parallel instruction structures, pushing down bus frequencies in scheduler calls of specific tasks.

• A phenomenal number of ASICs (80%) fail actually due to IP integration. And this boiled down to lazy designers just handing over RTL code. Now that's really funny because it's something I used to have discussions with while I worked at Nijmegen. Some hardware designers thought that their work finished at design level. Yeah they were the artists. It(s only now that the industry realises the need for proper wrappers around IP which allows third party designers or integrators to extract IP specific data. Now that's really funny. Cadence started this and now D&R is promoting some XML wrappers for IP. Is this a space which could be interesting for data quality and heuristic tool vendors ?

• The next big thing which will hit the industry is the Network On chip. There's just too much going on in this space to not take it seriously. But when I see how many teams presented their research work, I also believe that start ups like Silistix and Arteris are going to have a hard time and basically the big boys will use them as bargaining sticks with respect to internal design teams to get them faster to mature solutions.